Trial and error

젤 좋은건 뒤에 안붇은것들.. interface만 다름. 확인하고 구입하시길 바래요~

1.

Description Resource Path Location Type

address 0xa1bc of GGA.elf section `.bss' is not within region `onchip_memory2_0' GGA C/C++ Problem

Error (170040): Can't place all RAM cells in design

Info (170034): Selected device has 16 memory locations of type M144K block. The current design requires 24 memory locations of type M144K block to successfully fit.
Info (170033): Memory usage required for the design in the current device: 5% M9K block memory block locations required; 150% M144K block memory block locations required
 Info (170043): The Fitter setting for Equivalent RAM and MLAB Paused Read Capabilities is currently set to Care. More RAMs may be placed in MLAB locations if a different paused read behaviour is allowed.

- 메모리 너무 많음 줄여주셍 

slf2hex --input==*.elf --output=*.hex -- base=0x** --end=0x** --width=**

0. nios command shell 킨다음..

1. elf 파일있는데 까지 찾아가서

2. 위 와 같이 쳐주고,~ elf 파일 가져다 hex 만들거니 파일이름 입력해주고

3. base address From On-chip Memory 번지수 시작번지

  end Address From On-chip Memory 번지수 

4. Onchip Memory설정의 width 찾아서 입력해주고 그럼 끝

이렇게 명시 되어있네요 @ alt_types.h

#ifndef ALT_ASM_SRC
typedef signed char  alt_8;
typedef unsigned char  alt_u8;
typedef signed short alt_16;
typedef unsigned short alt_u16;
typedef signed long alt_32;
typedef unsigned long alt_u32;
typedef long long alt_64;
typedef unsigned long long alt_u64;
#endif

나름 자료형 정리한거..빈거는 댓글로 채워주세요~ 난중 채워서 올릴께요~


밑 Table1은 아래 Altera 사이트에서~
https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/nios2/n2cpu_nii51016.pdf

Reasons for Using a Bridge 

When you have no bridges between master-slave pairs, SOPC Builder generates a system interconnect fabric with maximum parallelism, such that all masters can drive transactions to all slaves concurrently, as long as each master accesses a different slave. For systems that do not require a large degree of concurrency, the default behavior might not provide optimal performance. With knowledge of the system and application, you can optimize the system interconnect fabric by inserting bridges to control the system topology.

Figure 11–2 and Figure 11–3 show an SOPC system without bridges. This system includes three CPUs, a DDR SDRAM controller, a message buffer RAM, a message buffer mutex, and a tristate bridge to an external SRAM. 

Figure 11–3 illustrates the default system interconnect fabric for the system in Figure 11–2. 

Figure 11–4 and Figure 11–5 show how inserting bridges can affect the generated logic. For example, if the DDR SDRAM controller can run at 166 MHz and the CPUs accessing it can run at 120 MHz, inserting an Avalon-MM clock-crossing bridge between the CPUs and the DDR SDRAM has the following benefits: 

■ Allows the CPU and DDR interfaces to run at different frequencies. 

■ Places system interconnect fabric for the arbitration logic and multiplexer for the DDR SDRAM controller in the slower clock domain. 

■ Reduces the complexity of the interconnect logic in the faster domain, allowing the system to achieve a higher fMAX. 

Inserting the clock-crossing bridge does increase read latency and may not be beneficial unless your system includes more devices that access the memory.

In the system illustrated in Figure 11–4, the message buffer RAM and message buffer mutex must respond quickly to the CPUs, but each response includes only a small amount of data. Placing an Avalon-MM pipeline bridge between the CPUs and the message buffers results in the following benefits: 

■ Eliminates separate arbiter logic for the message buffer RAM and message buffer mutex, which reduces logic utilization and propagation delay, thus increasing the fMAX. 

■ Reduces the overall size and complexity of the system interconnect fabric. 

If an orange triangle appears next to an address in Figure 11–4, it indicates that the address is an offset value and is not the true value of the address in the address map

Figure 11–5 shows the system interconnect fabric that SOPC Builder creates for the system in Figure 11–4. Figure 11–5 is the same system that is pictured in Figure 11–3 with bridges to control system topology